Semiconductor memory device

ABSTRACT

Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional status memory is provided.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and,particularly, to an SRAM alternative memory replaceable with a staticrandom access memory (SRAM), having compatibility with an SRAM. Moreparticularly, the invention relates to the configuration for setting anSRAM alternative memory into a specific mode.

2. Description of the Background Art

In an application of portable equipment, an SRAM is used as an internalmemory because of its high processing speed. A memory cell of the SRAMis constructed of four transistors and two load elements, and theoccupying area of the SRAM cell is large. Therefore, it is difficult toimplement a memory of a large storage capacity in a limited area.

As the functions of portable equipment are enhanced, it is necessary toprocess image data and audio data. The amount of data to be processedbecomes enormous and a memory of a large storage capacity is required asa memory device for the portable equipment. When using an SRAM as theinternal memory, it is difficult to implement the memory of a largestorage capacity in a small occupying area, so that a requirement ofdown-sizing and lightening high-function portable equipment cannot bemet.

On the other hand, the memory cell of a dynamic random access memory(DRAM) is constructed of one transistor and one capacitor in general.The DRAM has, therefore, an advantage that the occupying area of thememory cell is smaller than that of the SRAM. The DRAM is suitable forconstructing a memory of a large storage capacity in a small occupyingarea. However, the DRAM stores data in the capacitor and the stored datais lost by a leak current, so that refreshing operation for holdingstored data has to be periodically performed. During execution of therefreshing, an external device such as a processor cannot access theDRAM and is kept in a wait state, so that the processing efficiency ofthe system is lowered.

The DRAM is designated of a sleep mode and held in a standby state in awaiting time in portable equipment or the like. Also in the sleep mode,however, stored data has to be held and has to be periodicallyrefreshed. Therefore, an ultra low standby current condition of theorder of μA in the sleep mode required in a specification or the likecannot be satisfied.

In order to implement the memory of a large storage capacity with asmall occupying area, a DRAM-based memory has to be used. In the case ofusing such a DRAM-based memory (hereinbelow, called an SRAM alternativememory), the memory has to be replaced without significantly changingthe conventional system configuration. That is, compatibility of pins isrequired. Here, the “memory” indicates a memory device connected to adevice such as an external processor via pin terminals.

Different from a synchronous memory operating synchronously with a clocksignal such as a system clock, an SRAM operates statically according toan external control signal. In order to prevent the load of the externalprocessor from increasing, the SRAM alternative memory is required tooperate under the same operating conditions (signal timings) as those ofthe SRAM.

Particularly, in the case of designating various operation modes in theSRAM alternative memory, in view of compatibility of pins, the operationmodes have to be set by using signals prepared for a conventional SRAM.Particularly, as for designation of an operation mode which is notprepared for the conventional SRAM, signals used in the SRAM aregenerally a chip enable signal CE, an output enable signal OE, and awrite enable signal WE, and therefore, a complicated signal timingrelation cannot be used for setting a specific operation mode. In thecase of designating a specific operation mode with a relation of thetimings of signals different from the timings of signals used in ageneral SRAM, an external device such as a memory controller has to beprovided with a new function. Consequently, compatibility with aconventional SRAM cannot be maintained, and a load on the externaldevice increases.

SUMMARY OF THE INVENTION

An object of the invention is to provide an SRAM alternative memoryhaving pin compatibility with an SRAM.

Another object of the invention is to provide a semiconductor memorydevice capable of designating an internal operation mode by usingsignals similar to those used for an SRAM.

Still another object of the invention is to provide a semiconductormemory device capable of designating a specific operation modeasynchronously with a clock signal without increasing the number of pinterminals.

Further object of the invention is to provide a semiconductor memorydevice having a circuit for setting a command entry mode for designatinga specific operation mode by using an interface compatible with an SRAM.

A semiconductor memory device according to a first aspect of the presentinvention includes: mode detecting circuitry for detecting that externalsignals of a predetermined set are applied in a combination of specificlogic states a predetermined number of times successively; and modesetting circuitry for setting a specific mode in response to a detectionsignal from the mode detecting circuitry.

A semiconductor memory device according to a second aspect of theinvention is a semiconductor memory device accessed in accordance withan external signal in a normal operation mode, and includes a commanddecoder that is made active in a specific mode to decode a plurality ofpredetermined external signals out of the external signals forgenerating a signal for setting an internal state to a predeterminedstate. The command decoder generates a signal for designating anoperation related to a standby state.

A semiconductor memory device according to a third aspect of the presentinvention is a semiconductor memory device accessed in accordance withan external signal in a normal operation mode, and includes modedetecting circuitry for detecting that a predetermined set of externalsignals out of the external signals is applied in a combination ofspecific logic states a predetermined number of times successively; modesetting circuitry for setting a specific mode in response to a detectionsignal of the mode detecting circuitry; and a command decoder that ismade active in accordance with an output signal of the mode settingcircuitry to decode a plurality of predetermined external signals out ofthe external signals for generating a signal for setting an internalstatus to a predetermined status. The command decoder generates a signalfor designating an operation related to a standby state.

By setting the internal state in accordance with the states ofpredetermined external signals, the internal state can be set into adesired state by using signals of a conventional SRAM. Thus, asemiconductor memory device having compatibility with a convention SRAMcan be implemented.

By the construction that the semiconductor memory device enters aspecific mode when a specific state is executed a predetermined numberof times successively, the semiconductor memory device can be preventedfrom entering the specific mode erroneously in the normal mode. Thus, astably operating semiconductor memory device can be implemented.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically showing the entire configuration of asemiconductor memory device according to a first embodiment of theinvention;

FIG. 2 is a signal waveform diagram representing data reading operationof the semiconductor memory device shown in FIG. 1;

FIG. 3 is a signal waveform diagram representing data writing operationof the semiconductor memory device as shown in FIG. 1;

FIG. 4 is a diagram schematically showing the configuration of a modecontrol circuit shown in FIG. 1;

FIG. 5A is a diagram schematically showing the configuration of acommand mode detecting circuit shown in FIG. 4;

FIG. 5B is a diagram schematically showing the configuration of a shiftregister shown in FIG. 5A;

FIG. 6 is a timing chart representing operation of the command modedetecting circuit shown in FIGS. 5A and 5B;

FIG. 7 is a diagram showing status transition upon command mode entry;

FIG. 8 is a diagram schematically showing the configuration of a modedecoding circuit shown in FIG. 4;

FIG. 9 is a timing chart representing operation of the mode decodingcircuit shown in FIG. 8;

FIG. 10 is a diagram showing a specific example of the configurations ofa shift register, a command decoder, and a command setting circuit shownin FIG. 8;

FIG. 11 is a diagram showing status transition in a command mode of thesemiconductor memory device according to the invention;

FIG. 12 is a flowchart representing a wake-up sequence of thesemiconductor memory device according to the invention;

FIG. 13 if a flowchart representing a power-up sequence of thesemiconductor memory device according to the invention;

FIG. 14 is a diagram schematically showing the configuration of aportion related to power-down of a status control circuit shown in FIG.1;

FIG. 15 is a diagram schematically showing the configuration of aportion related to software resetting of the status control circuit asshown in FIG. 1;

FIG. 16 is a signal waveform diagram representing operation of thestatus control circuit as shown in FIG. 15;

FIG. 17 is a diagram schematically showing the configuration of a memorycell array in the semiconductor memory device according to theinvention;

FIG. 18 is a diagram schematically showing the configuration of aportion related to refreshing in an internal control signal generatingcircuit shown in FIG. 1;

FIG. 19 is a diagram schematically showing the configuration of arefresh block address generating circuit shown in FIG. 18;

FIG. 20 is a diagram schematically showing the configuration of aregister stage in a shift register with bypassing function shown in FIG.19;

FIG. 21 is a diagram schematically showing the configuration of a blockaddress register circuit shown in FIG. 19; and

FIG. 22 is a diagram schematically showing the configuration of a mainportion of a command mode detecting circuit according to a secondembodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1 is a diagram schematically showing the entire configuration of asemiconductor memory device according to a first embodiment of thepresent invention. In FIG. 1, a semiconductor memory device 1 includes:a memory cell array 2 having a plurality of memory cells arranged in amatrix; a row address buffer 3 receiving address signal bits A7 to A19from an outside and generating an internal row address signal RA; acolumn address buffer 4 receiving address signal bits A0 to A6 from theoutside and generating an internal column address signal CA; a rowdecoder 5 for decoding internal row address signal RA and selecting arow in memory cell array 2; a column decoder 6 for decoding internalcolumn address signal CA and generating a column selection signal forselecting a column in memory cell array 2; a sense amplifier for sensingamplifying and latching data of memory cells on the row selected by rowdecoder 5; and an I/O gate for connecting the selected column in memorycell array 2 to an internal data line (I/O line) in accordance with thecolumn selection signal from column decoder 6. In FIG. 1, the senseamplifier and the I/O gate are indicated by a block 7.

Semiconductor memory device 1 further includes: a lower-order inputbuffer 8 for writing lower byte data DQ0 to DQ7 in data writingoperation; a lower-order output buffer 9 for outputting the lower bytedata to an outside in data reading operation; a higher-order inputbuffer 10 for receiving upper byte data DQ8 to DQ15 and generatinginternal write data in data writing operation; a higher-order outputbuffer 11 for outputting upper byte data DQ8 to DQ15 in data readingoperation; and an internal control signal generating circuit 12 forgenerating signals for controlling various internal operations inaccordance with externally applied control signals, such as a chipenable signal CE#, an output enable signal OE#, a write enable signalWE#, a lower byte enable signal LB#, and an upper byte enable signalUB#.

When chip enable signal CE# is at the L level, it instructs thatsemiconductor memory device 1 is selected, and semiconductor memorydevice 1 can be accessed. When output enable signal OE# is at the Llevel, a data reading mode is designated. When write enable signal WE#is at the L level, a data writing mode is designated. When lower byteenable signal LB# is at the L level, it instructs that lower byte dataDQ0 to DQ7 is valid. When upper byte enable signal UB# is at the Llevel, it instructs that upper byte data DQ8 to DQ15 is valid.

Internal control signal generating circuit 12 controls the operations ofrow address buffer 3, column address buffer 4, row decoder 5, columndecoder 6, and sense amplifier/IO gate block 7 in accordance with chipenable signal CE#, output enable signal OE#, and write enable signalWE#. Internal control signal generating circuit 12 further controls theactive/inactive state of each of lower-order input buffer 8, lower-orderoutput buffer 9, higher-order input buffer 10, and higher-order outputbuffer 11 in accordance with upper byte enable signal UB# and lower byteenable signal LB#, depending on the designated operation mode.

Semiconductor memory device 1 further includes: a mode control circuit20 receiving control signals CE#, OE#, and WE#, address signals A0 toA19, and data bits DQ0 to DQ15, for setting semiconductor memory device1 into a specific operation mode; and a status control circuit 22 forsetting the internal status of semiconductor memory device 1 into adesignated status in accordance with a mode setting signal MD from modecontrol circuit 20. The configuration of mode control circuit 20 will bedescribed in detail later.

When semiconductor memory device 1 is accessed in an access sequencethat is not used in a normal access mode, semiconductor memory device 1enters a command mode for accepting a command of designating a specificinternal status. In this state, a command designating an internal statusis supplied by using data bits DQ0 to DQ15, with a specific addressdesignated. According to the decoding result of the command, internalstatus setting signal (mode setting signal) MD is generated.

Status control circuit 22 sets the internal status to, for example, aninitial status or a power-down status in accordance with status controlsignal MD from mode control circuit 20. Status control circuit 22 setsan internal status related to an operation mode required of low powerconsumption such as a standby status. The configurations of thesecircuits will be described in detail later. By using an external commandfor setting the internal status, it becomes unnecessary to use adedicated pin terminal for designating a status such as a power-downstatus. With the same signal timing relationship as that in the normaloperation mode for accessing data, a desired operation mode can bedesignated. An external memory controller or the like can designate adesired operation mode only by changing a program. It is unnecessary tosignificantly change the internal configuration of a conventionalexternal device, and compatibility with a conventional memory can beeasily maintained.

FIG. 2 is a signal waveform diagram representing data reading operationof semiconductor memory device 1 shown in FIG. 1. In FIG. 2, chip enablesignal CE# is set to the L level, and upper byte enable signal UB# andlower byte enable signal LB# for designating upper byte data and lowerbyte data, respectively, are set selectively to the L level inaccordance with data bits to be read. In this state, address signal bitsA0 to A19 are set and, subsequently, output enable signal OE# is set tothe L level. Write enable signal WE# is maintained at the H level.

By using the falling to the L level of output enable signal OE# as atrigger, under control of internal control signal generating circuit 12,row address buffer 3 and column address buffer 4 take in externallyapplied address signal bits A19 to A0 and generate internal row addresssignal RA and internal column address signal CA, respectively. Accordingto internal row address signal RA and internal column address signal CA,row decoder 5 and column decoder 6 perform decoding operation atpredetermined timings under control of internal control signalgenerating circuit 12, memory cells are selected, and data of theselected memory cells are read out.

When upper byte enable signal UB# is at the H level, upper byte data DQ8to DQ15 enters a high impedance state. When lower byte enable signal LB#is set to the L level, valid data is read as lower byte data DQ0 to DQ7.The external data maintains the valid state for a period since outputenable signal OE# goes high until the output circuit is set in a disablestate.

FIG. 3 is a signal waveform diagram representing data writing operationof semiconductor memory device 1 shown in FIG. 1. As shown in FIG. 3,also in the data writing operation, according to upper byte enablesignal UB# and lower byte enable signal LB#, validity/invalidity ofupper byte data and lower byte data is designated. When chip enablesignal CE# is at the low level, semiconductor memory device 1 can beaccessed. In the data writing operation, write enable signal WE# islowered to the L level. By using the falling of write enable signal WE#as a trigger, externally applied address bits A19 to A0 are taken intothe inside, internal row address signal RA and internal column addresssignal CA are generated accordingly, and a memory cell selectingoperation is performed by row decoder 5 and column decoder 6 shown inFIG. 1. Data bits DQ0 to DQ15 supplied externally are selectivelywritten internally in accordance with upper byte enable signal UB# andlower byte enable signal LB#.

Data bits DQ0 to DQ15 are required of a setup time tsu and a hold timethd relative to the rising edge of write enable signal WE#.Semiconductor memory device 1 shown in FIG. 1 is a DRAM-basedsemiconductor memory device in which row selecting operation and columnselecting operation are executed time-division-multiplexedly. When adata access is designated by write enable signal WE# or read enablesignal OE#, a row address signal and a column address signal areinternally generated in accordance with an address signal externallyapplied. Upon selection of a memory cell, the row selecting operation isperformed first, and memory cell data is latched by the sense amplifier.Subsequently, the column selecting operation is performed and data ofthe selected memory cell is read or data is written to the selectedmemory cell.

Write enable signal WE# has to be maintained at the L level for theperiod in which the column selecting operation is performed. In order towrite data into the selected memory cell through the column selectingoperation, the setup time tsu is required for external data bits DQ0 toDQ15. Hold time thd may be therefore 0 ns (nano second) at the minimum.

As shown in the timing charts of FIGS. 2 and 3, semiconductor memorydevice 1 shown in FIG. 1 takes in externally applied address signals inaccordance with chip enable signal CE#, output enable signal OE#, andwrite enable signal WE#, and writes or reads data. The control signalsused in semiconductor memory device 1 are the same as those used in anSRAM. Therefore, the interface of semiconductor memory device 1 hascompatibility with an SRAM.

When an access is made in a sequence different from a normal accesssequence in accordance with external control signals CE#, OE#, and WE#and address signal bits A0 to A19, mode control circuit 20 determinesthat a mode (command mode) for designating a specific operation mode isdesignated. In the command mode, mode control circuit 20 controls aninternal operation status in accordance with an external signal(command). Specifically, when a specific access sequence is executed,the command mode is set to allow acceptance of external applied command.In the command mode, when a signal such as a data bit applied externallyis written with a specific address designated, the external signal istaken in as a command, and the internal status is set to a statusdesignated by the command.

FIG. 4 is a diagram schematically showing the configuration of modecontrol circuit 20 shown in FIG. 1. In FIG. 4, mode control circuit 20includes: a command mode detecting circuit 30 receiving external controlsignals CE#, OE#, and WE# and address signal bits A19 to A0 and, whenthe signals are supplied in a predetermined sequence, generating acommand mode entry signal CMERY; and a mode decoding circuit 32 that isactivated when command entry signal CMERY is made active, for taking inand decoding predetermined bits in data bits DQ0 to DQ15 as a commandand generating mode setting signal MD in accordance with the result ofdecoding.

When address signal bits A19 to A0 designate a specific address and anaccess is made a predetermined number of times successively, commandmode detecting circuit 30 activates command mode entry signal CMERY.Specifically, as an example, when data is read from the final address(FFFFFH) four times successively, command mode detecting circuit 30activates command mode entry signal CMERY. When command mode entrysignal CMERY is made active, mode decoding circuit 32 enters an externalcommand acceptable state.

In the normal operation mode, it is very rare to read data from the sameaddress four times successively. Particularly, the final address is notgenerally used so much. By setting the command mode when an access ismade in a access sequence different from that in the normal access mode,without using a complicated signal timing relationship, the command modecan be reliably designated only with the signal timing relationship asthat in the normal operation mode.

Even when valid data is stored in the final address, the read mode ismerely designated, and therefore, the data stored in the final addressis just read in the command mode entry and is not destructed.

FIG. 5A is a diagram schematically showing an example of theconfiguration of command mode detecting circuit 30 shown in FIG. 4. InFIG. 5A, command mode detecting circuit 30 includes: a decoding circuit30a for decoding address signal bits A0 to A19; a read mode detectingcircuit 30b receiving output enable signal OE# and chip enable signalCE# and activating, when the data read mode is designated, a read modeinstruction signal φrz; a write mode detecting circuit 30c receivingchip enable signal CE# and write enable signal WE# and driving, when thedata write mode is designated, a write mode instruction signal φwz tothe L level; a shifter 30d for sequentially transferring an outputsignal FAD of address decoding circuit 30a in accordance with read modeinstruction signal φrz from read mode detecting circuit 30b; a sequencedecoding circuit 30e for decoding output bits Q1 to Q4 of shifter 30d;and a flip flop 30f that is set when the output signal of sequencedecoding circuit 30e is at the H level. Command mode entry signal CMERYis generated from flip flop 30f.

Address decoding circuit 30a sets decode signal FAD to the H level whenall of address signal bits A19 to A0 are “0”. That is, when the finaladdress “FFFFFH” is designated, decode signal FAD is set to the H level.Read mode detecting circuit 30b sets read mode instruction signal φrz tothe L level when both output enable signal OE# and chip enable signalCE# are in the active state of the L level. Write mode detecting circuit30c sets write mode instruction signal φwz to the L level when bothwrite enable signal WE# and chip enable signal CE# are in the activestate or the L level.

Shifter 30d includes cascaded D latches 30da to 30de of four stages asshown in FIG. 5B. When read mode instruction signal φrz goes low, eachof D latches 30da to 30de takes in a signal received at its input. Whenread mode instruction signal φrz goes high, each of D latches 30da to30de enters a latch state of latching and outputting the taken insignal. When write mode instruction signal φwz goes low, output databits Q1 to Q4 of D latches 30da to 30de are reset to “0”.

When all output bits Q1 to Q4 of shifter 30d is set high, sequencedecoding circuit 30e sets the output signal to the H level to set/resetflip flop 30f, thereby driving command mode entry signal CMERY to the Hlevel. Set/reset flip flop 30f is reset by a reset signal RST generatedwhen a command mode exit command or the like is supplied.

Flip flop 30f is used for the following reason. That is, operation modesdesignated upon entry into the command mode include a mode of readingdata in a memory block designated as a data holding block, as will bedescribed later, and data reading operation may be designated. In thecommand entry mode, therefore, a command is not always written.

FIG. 6 is a timing chart representing an operation of command modedetecting circuit 30 shown in FIGS. 5A and 5B. With reference to FIGS.5A, 5B, and 6, the operation of command mode detecting circuit 30 willbe described below.

All of address signal bits A0 to A19 are set to the H level to designatethe final address FFFFFH. Subsequently, output enable signal OE# is setto the L level to instruct the data read mode. Since chip enable signalCE# is at the L level, when the data read mode is designated, read modeinstruction signal φrz from read mode detecting circuit 30b goes low,and shifter 30d takes in decode signal FAD from decoding circuit 30a.When output enable signal OE# is once set to the H level, the data readmode is completed.

The semiconductor memory device shown in FIG. 1 is a DRAM-basedsemiconductor memory device. By output enable signal OE#, one accesscycle for performing row selection and column selection is specified. Tocomplete an access cycle, output enable signal OE# is once set to the Hlevel. When output enable signal OE# goes high, read mode instructionsignal φrz from read mode detecting circuit 30b goes high, shifter 30dperforms shifting operation, and output bit Q1 of shifter 30d is set tothe H level. Specifically, each of D latches 30da to 30de shown in FIG.5B takes in a signal applied to its input when read mode detectionsignal φrz is at the L level and outputs the taken in signal from itsoutput, and enters a latch state when read mode instruction signal φrzgoes high.

Subsequently, the operation of reading data in final address FFFFFH isperformed four times. In response to the rising of read mode detectionsignal φrz, all of output bits Q1 to Q4 of shifter 30d go high, andaccordingly, set/reset flip flop 30f is set to set command mode entrysignal CMERY to the H level. The semiconductor memory device isconsequently set into the command mode.

Final address FFFFFH is hardly accessed in the normal operation mode,and data is rarely read from the same address four times successively inthe normal operation mode. What can be considered at most is a mode ofreading upper byte data and lower byte data from the final address. Inthis case, data is read from the final address only twice successively.Therefore, data is not read from the final address four timessuccessively in the normal operation cycle, so that the semiconductormemory device can be set reliably into the command mode without exertingan adverse influence on the operation in the normal operation mode.

In the case where the data writing operation mode is designated at thetime of command mode entry, write mode instruction signal φwz goes low,shifter 30b is reset, and all of output bits Q1 to Q4 go low. In thiscase, the command mode entry operation has to be executed again from thebeginning.

In the case of reading data with an address different from the finaladdress designated in the command mode entry, decode signal FAD outputfrom address decoding circuit 30a is set to L level. In this case, oneof bits Q1 to Q4 of shifter 30d is set to L level until data is readfrom the final address four times successively. Therefore, only whendata is read from the final address four times successively, commandmode entry signal CMERY can be set to the H level. Thus, an access madein a sequence different from that in the normal operation mode can beidentified to designate the command mode.

A command mode is set using the signals similar to those used for anSRAM, that is, chip enable signal CE#, output enable signal OE#, writeenable signal WE# and address signals. The command mode can be setasynchronously with a clock signal such as a system clock signal. Thus,a command mode can be set using an interface compatible with an SRAM.

Address signal bits A0 to A19 supplied to decoding circuit 30a may besignals from row address buffer 3 and column address buffer 4 shown inFIG. 1. When output enable signal OE# goes low, each of address buffers3 and 4 takes in an address signal and generates an internal addresssignal. Address signal bits A0 to A19 to decoding circuit 30a may besignals generated via a mere input buffer circuit.

FIG. 7 is a diagram showing status transition upon command mode entry ofthe semiconductor memory device according to the first embodiment of theinvention. Referring to FIG. 7, the status transition at the time ofcommand mode entry will be briefly described below.

In a normal read/write status ST0 in which normal data reading/writingoperation is performed, an instruction of reading data from addressFFFFFH (Hex) is applied. By the operation of reading data from the finaladdress, the status shifts to a command mode setup status ST1. Incommand mode setup status ST1, operation of reading data from the finaladdress is executed again. The status shifts to the subsequent commandmode setup status ST2 where an instruction of reading the data from thefinal address is applied again. Then, the status shifts to a finalcommand mode setup status ST3. After the data in the final address isread again in the final command mode setup status ST3, semiconductormemory device 1 enters a command mode and a command standby status ST4of waiting for a command is set.

In the case where an access different from that of reading data from thefinal address is made in any of setup statuses ST1 to ST3, the commandmode setup is reset, and the status is reset to normal read/write statusST0.

FIG. 8 is a diagram schematically showing the configuration of modedecoding circuit 32 shown in FIG. 4. In FIG. 8, at the preceding stageof mode decoding circuit 32, an input/output buffer 40 forinputting/outputting external data DQ0 to DQ7 and an input buffer 41 forreceiving external control signals CE#, WE#, and OE# are provided.Input/output buffer 40 corresponds to input buffer 8 and output buffer 9shown in FIG. 1. Input buffer 41 buffers chip enable signal CE#, writeenable signal WE#, and output enable signal OE# externally applied togenerate an internal chip enable signal CE, an internal write enablesignal WE, and an internal output enable signal OE. Internal chip enablesignal CE, internal write enable signal WE, and internal output enablesignal OE are each set to the H level when activated.

More decoding circuit 32 includes: an NAND circuit 42 receiving internalchip enable signal CE and internal write enable signal WE; an NANDcircuit 43 receiving internal chip enable signal CE and internal outputenable signal OE; an NAND circuit 44 receiving output signals from NANDcircuits 42 and 43; an AND circuit 45 receiving an output signal of NANDcircuit 44 and command mode entry signal CMERY and generating a pulsesignal PLS; a shift register 47 for sequentially transferring receiveddata in accordance with pulse signal PLS; a bus switching circuit 46 forconnecting input/output buffer 40 to either an internal write/readcircuit or shift register 47 in accordance with command mode entrysignal CMERY; a command decoder 48 for decoding data output from shiftregister 47; and a command setting circuit 49 for latching an outputsignal of command decoder 48 and generating an internal operation modeinstruction signal in accordance with decode signal FAD from the addressdecoding circuit shown in FIG. 5A and pulse signal PLS.

In the command mode, lower byte data DQ0 to DQ7 is used as a command andupper byte data DQ8 to DQ15 is not used. In the command mode, theapplication of the command is detected by decode signal FAD. Therefore,for example, when data is written with an address other than the finaladdress designated in the command mode, a command is not taken in.

The internal write/read circuit includes a preamplifier and a writedriver and transmits/receives internal data to/from a selected memorycell in the memory cell array. When the command mode is designated, theinternal write/read circuit is disconnected from the input/outputbuffer, so that data is not written/read into/from the memory cellarray. In the command mode, the row/column selecting operation may beinhibited. In this configuration, the row/column selecting operation isinhibited by command mode entry signal CMERY. However, circuitry forreceiving the address signal and data is made operable. Alternatively,in the case of receiving data bits DQ0 to DQ7 and address signal bits A0to A19 via a mere buffer circuit to perform the command mode entry andthe command mode setting, since the buffer circuits operateasynchronously with an external control signal, all of circuits forexecuting an normal access related to the row and column selection maybe set, in the command mode, to an operation stopped stated (standbystate) in accordance with command mode entry signal CMERY.

According to an output signal of command decoder 48, command settingcircuit 49 generates: an exit instruction signal EXIT for completing thecommand mode and making transition to the normal operation mode; a powerdown instruction signal PWD for cutting off supply of power to internalcircuits; a wake up instruction signal WKU for completing the power downmode; a data holding block setup signal DHBS for designating a dataholding area; a data holding area reading instruction signal DHBR forreading information on the data holding block area; and a software resetsignal SFRST for setting the internal circuitry to the initial state.

Each of the power down mode, software reset mode, and data holding areadesignation designates a state related to the standby status of thesemiconductor memory device. In the case of holding the semiconductormemory device in the standby status for a long period, data in a dataholding area is held by specifying the data holding area. When the powerdown mode is set, data is not held.

The internal mode designating signals outputted from command settingcircuit 49 correspond to mode setting signal MD shown in FIG. 1.

FIG. 9 is a timing chart representing an operation of mode decodingcircuit 32 shown in FIG. 8. Referring to the timing chart of FIG. 9, theoperation of mode decoding circuit 32 shown in FIG. 8 will be brieflydescribed below.

In FIG. 9, an example is shown in which a command for designating anoperation mode consists of data D0 to D2 of three bytes.

In the command mode, command mode entry signal CMERY is at the H level.In command standby stage ST4, final address FFFFFH is designated anddata is written. When write enable signal WE# is activated, an outputsignal of NAND circuit 42 shown in FIG. 8 goes low and accordingly, anoutput signal of NAND circuit 44 goes high. Since command mode entrysignal CMERY is at the H level, pulse signal PLS from AND circuit 45goes high. Shift register 47 performs shifting operation in accordancewith pulse signal PLS and takes in data bits DQ7 to DQ0 supplied frombus switching circuit 46.

When command mode entry signal CMERY is activated, bus switching circuit46 connects input/output buffer 40 to shift register 47, and theinternal write/read circuitry is isolated from input/output buffer 40.That is, upon the command mode entry, data is not written/read to/from amemory cell. As stated above, this can be easily implemented by simplystopping the operation of internal control signal generating circuit 12shown in FIG. 1 in accordance with command mode entry signal CMERY.

When the final address is designated and data is written a plurality ofnumber of times, data D0, D1, and D2 are stored in shift register 47.Command decoder 48 normally decodes data stored in shift register 47.According to the data patterns of data D0 to D2, command decoder 48determines that the command for designating a specific operation mode issupplied and drives a corresponding internal mode instruction signal tothe H level.

When pulse signal PLS is applied and address decode signal FADindicating that the final address is specified goes high, commandsetting circuit 49 drives the corresponding internal mode designatingsignal to the active state of the H level in accordance with the outputsignal of command decoder 48.

Also in the case where the data reading operation is designated when thecommand mode is set, pulse signal PLS is made active. In this case,shift register 47 performs shifting operation and takes in and transfersdata applied via bus switching circuit 46. In this case, therefore, fora command other than the data holding area reading command, data quitedifferent from the command is taken in shift register 47, and an outputsignal of command decoder 48 maintains an inactive state.

Pulse signal PLS is generated also in the data read mode for the purposethat when data holding block reading mode DHBR is designated, the readmode is designated and the data holding block specifying signal storedin a not-shown register is read via the output buffer circuit. Throughthe shifting operation of shift register 47, the data holding area readcommand is supplied to command decoder 48, and data holding area readinstruction signal DHBR goes high. Responsively, the data stored in theregister for storing the data holding area specifying data is read out.

FIG. 10 is a diagram showing an example of the specific configuration ofshift register 47, command decoder 48, and command setting circuit 49shown in FIG. 8. In FIG. 10, shift register 47 includes registercircuits 47a to 47c each having a 1-byte register stage. Registercircuits 47a to 47c perform shifting operation on a byte basis inaccordance with pulse signal PLS. Accordingly, a group of data bits DQ7to DQ0 from bus switching circuit 46 shown in FIG. 8 is sequentiallytransferred through register circuits 47a, 47b, and 47c in accordancewith pulse signal PLS.

Command decoder 48 includes a decoding circuit 48a provided incorrespondence with each operation mode designate signal. In FIG. 10,decoding circuit 48a receives data bits of register circuits 47a to 47cand sets its output signal to the H level when the received data bitsare in a specific predetermined combination in logic level. Depending onan operation mode to be designated, the command is constructed by bytedata, or the command is constructed by two-byte data. According to theconfiguration of each command, the decoding circuit is provided.

Command setting circuit 49 includes a trigger signal generating circuit49a for generating a trigger signal in accordance with decode signal FADindicative of designation of the final address and pulse signal PLS; anda latch circuit 49b for taking in and latching an output signal ofcorresponding command decoding circuit 48a in accordance with an outputsignal of trigger signal generating circuit 49a. Trigger signalgenerating circuit 49a is formed of, for example, an AND circuit, andoutputs an H level signal when both decode signal FAD and pulse signalPLS are at the H level.

Latch circuit 49b includes: a transfer gate 50a which is made conductivein accordance with an output signal of trigger signal generating circuit49a; an inverter 50b for inverting a corresponding command decode signalsupplied via transfer gate 50a; an inverter 50d for inverting an outputsignal of inverter 50b to generate a mode designation signal MDa; and aninverter 50c for inverting an output signal of inverter 50b andtransmitting the inverted signal to the input of inverter 50b.

When the output signal of trigger signal generating circuit 49a goeshigh, latch circuit 49b enters a through state, takes in and latches acorresponding output signal of command decoding circuit 48a, and drivesmode designation signal MDa to the H level or an active state.Consequently, by providing latch circuit 49b for each of modedesignation signals EXIT, PWD, WKU, BHBS, DHBR, and SFRST, each modedesignation signal can be generate to set a designated operation mode.

Even by providing trigger signal generating circuit 49a commonly for theplurality of mode designating signals, two operation modes are notexecuted simultaneously, and therefore, there causes no problem. Forexample, in order to complete the power down mode, it is necessary tosupply the exit command to activate exit mode instructing signal EXT. Inthis case, power down mode instructing signal PWD is made inactive.Thus, no problem occurs.

It is also possible to dispose a flip flop in correspondence with eachcommand and to set the flip flop when a corresponding command issupplied. For example, the flip lop has only to be reset by applying thewake up command, exit command, or reset command, or by designating theend of the command mode.

Specifically, in command setting circuit 49 shown in FIG. 10, in placeof latch circuit 49b, a set/reset flip flop may be used. For example,when the exit command or software reset command SFRST is supplied,command setting circuit 49 is reset. It is sufficient to reset the flipflop when an appropriate command is applied in accordance with theoperation mode designated by the command setting circuit.

FIG. 11 is a diagram showing transition of the internal status uponsetting of the command mode. Since a command is set by designating theoperation of writing data to the final address FFFFFH, only dataconstructing a command is shown in FIG. 11. In the case of designatingthe final address and writing data B1H in command standby status ST4,the status shifts to software power down setup status ST5. Since it isin the command mode, data is not written to the memory cell array(memory array is held in the standby state).

Subsequently, when the final address is designated again andpredetermined data DOH is written, the status shifts to a software powerdown status ST6. In software power down status ST6, power downinstructing signal PWD from the command setting circuit becomes activeand the power supply to the internal circuitry is shut off. When thepower down operation is completed, the status shifts to a commandstandby status ST7 for waiting for a next command in the power downstate of the internal circuitry. Command standby status ST7 is a powerdown status in which the power supply to circuits except for modecontrol circuit 22 (including the input buffer circuit) shown in FIG. 1is shut off.

In the case of writing data FAH with the final address designated incommand standby status ST7, the status shifts to a wake up status ST8.In the wake up status ST8, the power down is completed and the power issupplied to the internal circuitry to which the power supply has beenshut off. After recovery of the power supply, the status shifts fromwake up status ST8 to command standby status ST4 for waiting for a nextcommand. The reason why the status does not shift from wake up statusST8 to normal read/write status ST0 after completion of the wake upoperation is that the internal state has to be initialized and a commandfor this initialization purpose has to be executed.

In the case of designating the final address for writing data D2H incommand standby status ST4, the status shifts to a software reset/setupstatus ST9. When data DOH is written with the final address designatedagain in software reset/setup status ST9, the status shifts to asoftware reset status ST10. In the software reset status ST10, theinternal, peripheral circuitry is initialized. After completion ofinitialization of the internal status in software resetting status ST10,the status shifts again to command standby status ST4. In software resetstatus ST10, in a manner similar to the power-on or power-up, aninternal node is initialized to a predetermined potential level inaccordance with a power-on detection signal. In the initialization, adummy cycle may be performed a predetermined number of times to operatethe internal circuitry, thereby setting the internal state to thestandby state with reliability as performed in a normal DRAM.

When the final address is designated and data FFH is written in commandstandby status ST4, the status shifts to an exit status ST11. In theexit status ST11, reset signal RST shown in FIG. 5A is reset, commandmode entry signal CMERY becomes inactive, command mode CM is completed,and the status shifts to normal read/write status ST0. Accordingly,normal data writing/reading operation can be performed subsequently. Atthis time, the command mode can be set up again.

On the other hand, in the case where the final address is designated anddata FFH is written in the command standby status ST7, the status shiftsagain to exit status ST11, the power down status is completed, and thestatus shifts to normal read/write status ST0. In this case, theinternal state is not initialized, so that software reset has to beperformed.

On the other hand, when the final address is designated and data D3H iswritten in command standby status ST4, the status shifts to a DHBselection setup status ST12. By designating the final address again andsetting data DHB for designating the data holding block area in DHBselection setup status ST12, the status shifts to a DHB selection setupstatus ST13.

When the final address is designated again and data DOH is written inthe status ST13, the data holding block area is set by data DHB, and thestatus shifts to a DHB write status ST14. In status ST14, data forspecifying the data holding area is written and the data holding area isdesignated.

After completion of setting the data holding block in status ST14, thestatus shifts again to command standby status ST4.

On the other hand, when the final address is designated and data 7DH iswritten in command standby status ST4, the status shifts to a DHB readsetup status ST15. In DHB read setup status ST15, the status of readingthe contents in the data holding block is set. When the data readingoperation is executed in the status ST15, the status shifts to a DHBread status ST16 where each data holding block information is read out.After completion of the DHB read status ST16, the status shifts again tocommand standby status ST4. By performing the DHB reading operation, amemory block which is designated to hold data can be confirmed.

In the setup statuses, in the case of making an access different from anaccess for designating an operation of writing data DOH to the finaladdress or reading data from the final data required to set any internalstatus, the status shifts again to command standby status ST4.

By designating the final address externally and writing the command viaa data terminal in command standby status ST4, the status can be easilyshifted from the setup status to the internal command executing status.Accordingly, various operation modes of the semiconductor memory device,particularly, operation modes related to initialization can be set whilemaintaining the compatibility of pins with a normal SRAM. Although thecommand is set by using the lower byte data DQ0 to DQ7, the upper bytedata DQ8 to dQ15 can be used in place of the lower byte data DQ0 to dQ7.Consequently, both setup of a command with the upper byte data and setupof a command with the lower byte data can be easily implementedaccording to the internal configuration.

FIG. 12 is a flowchart of a wake up sequence for completing the powerdown mode in the status transition diagram of FIG. 11. The wake upsequence will be briefly described below.

In command standby status ST7 as shown in FIG. 11, the semiconductormemory device 1 is in a software power down status (step STP0). Thisstatus shifts through statuses ST5 and ST6 shown in FIG. 11 to executethe wake up command (step STP1). By executing the wake up command, theinternal circuitry in the power down state enters a power up state(power supply voltage is supplied). The power is simply supplied and theinternal state is unstable. Therefore, in order to initialize theinternal states, passing through the statuses ST9 and ST10 shown in FIG.11, the software reset command is executed (step STP2). By executing thesoftware reset command, the internal states are initialized topredetermined states.

After initializing the internal states, the status shifts to a statusST11 shown in FIG. 11 where the exit command is executed (step STP3). Byexecuting the exit command, the command mode is completed and the statusreturns to the normal write/read status ST0 shown in FIG. 7. In stepSTP4 for performing a subsequent operation, either a data access in thenormal read/write operation or an operation of successively reading datafrom the final address to set the command mode again may be performed.

On the other hand, also in the case of executing the exit command insoftware power down status ST7 (step STP5), the command mode iscompleted and the power supply voltage is supplied to the internalcircuitry in the power down state. In the case of executing the exitcommand, simply, the command mode is completed, the power down status isreleased and the status shifts to normal write/read status ST0 shown inFIG. 7. Therefore, the internal state of the semiconductor memory deviceis unstable. Thus, the operation of successively reading data in thefinal address is again performed a predetermined number of times (fourtimes) to set the command mode (step STP6). After entering the commandmode, the process returns to step STP2 where the software reset commandis executed, and then subsequent steps STP3 and STP4 are executed.

The shift from the power down status to power up status is made bymerely executing a command, it is not required to externally set theinternal states in a hardware manner via a specific pin terminal, and inaddition, a special signal timing relationship is not necessary. Withthe terminal group used in the normal operation, through the samesetting of the states of the logic levels of the signals as in thenormal operation, the operation for initialization can be performed.

FIG. 13 is a flowchart showing an operation sequence at power up. Whenpower is up (step STP10), whether a power supply voltage VCC reaches apredetermined value or not is determined (step STP11). Whether the powersupply voltage VCC reaches the predetermined level or not is detectedby, for example, a power on detection signal POR output from an internalpower on detecting circuit (POR detecting circuit).

When it is detected in step STP11 that the power supply voltage VCCreaches the predetermined level, the device waits until the internalstate is stabilized, that is, until predetermined time of, for example,500 μs elapses (step STP12). After elapse of the predetermined time, thecommand mode entry operation is executed to enter the command mode (stepSTP13). By the command mode entry, mode decoding circuit 32 shown inFIG. 4 enters command standby status ST4 shown in FIG. 11. In thecommand mode, a software reset command is executed (step STP14). Byexecuting the software reset command, the internal state is initialized.The software reset command is executed, thereby reliably initializingthe internal state also in the peripheral circuitry which does notreceive power on detection signal POR.

Subsequently, the exit command is executed (step STP15) to exit thecommand mode and enter the normal mode where a following operation isperformed (step STP16). By the step STP16, setting of the normal modeafter power on is completed.

Therefore, also at initialization of the internal state after power on,the internal state can be reliably set to the initial state, using thenormal signals. This holds for the case of recovery of the power supplyvoltage from the shut off of the power supply voltage.

FIG. 14 is a diagram schematically showing the configuration of aportion related to the power down of status control circuit 22 shown inFIG. 1. In FIG. 14, status control circuit 22 includes: an OR circuit60a receiving wake up instruction signal WKU and exit instruction signalEXIT from mode control circuit 20; a set/reset flip flop 60b that is setwhen power down instruction signal PWD from mode control circuit 20 isactivated, and is reset when an output signal of OR circuit 60a goeshigh; and a power source transistor 60c for connecting a power supplymode to a power supply line 52 of a memory circuit 50 in accordance witha signal from an output Q of set/reset flip flop 60b. Power supplytransistor 60c is formed of, for example, a P-channel MOS transistor andis made non-conductive, when set/reset flip flop 60b is set, to isolatepower supply line 52 of memory circuit 50 from the power supply node.Memory circuit power supply line 52 includes power supply lines providedfor the peripheral circuitry and for the memory cell array in memorycircuit 50, that is, a peripheral power supply line and an array powersupply line.

To mode control circuit 20, power supply voltage VCC is normallysupplied. To a not shown input/output circuit (input/output circuit usedto designate the command mode) as well, the power supply voltage VCC issupplied also in the power down mode.

In the configuration of status control circuit 22 shown in FIG. 14, whenstatus control circuit 22 enters the power down mode, power downinstruction signal PWD goes high, set/reset flip flop 60b is set, and asignal from the output Q of the flip flop 60b goes high. Accordingly,power supply transistor 60c is made non-conductive to cut off the supplyof the power supply voltage VCC to power supply line 52 for memorycircuit 50. Memory circuit 50 includes memory cell array 2 shown in FIG.1 and its peripheral circuitry.

When a signal instructing writing/reading of data is applied to modecontrol circuit 20, in the case where the operation of the input bufferis controlled by internal control signal generating circuit 12, thepower supply voltage is also supplied to the input/output buffer circuitcontrol unit in internal control signal generating circuit 12. Theportion related to selection of row and column of the memory cell arrayis included in memory circuit 50 and the supply of the power supplyvoltage is cut off.

When the wake up command is applied, wake up instruction signal WKU goeshigh, an output signal of OR circuit 60a goes high, set/reset flip flop60b is reset to raise the signal from the output Q thereof to H level,power supply transistor 60c is made conductive, and the power supplyvoltage VCC is supplied to memory circuit 50.

When the exit command is applied, exit instruction signal EXIT goeshigh, an output signal of OR circuit 60a goes high, and similarly,set/reset flip flop 60b is reset. Accordingly, power supply transistor60c is made conductive, and accordingly the memory power supply line 52is connected to the power supply terminal and receives the power supplyvoltage VCC. A predetermined time is necessary until the voltage ofmemory power supply line 52 is stabilized and until the state of theinternal circuitry is stabilized.

FIG. 15 is a diagram schematically showing the configuration of aportion related to software reset in status control circuit 22 shown inFIG. 1. In FIG. 15, status control circuit 22 includes: a power ondetecting circuit 62a for detecting whether the power supply voltage VCCreaches a predetermined voltage level or not; and a gate circuit. 62breceiving power on detection signal POR from power on detecting circuit62a and software reset signal SFRST and generating a reset signal RSTT.Gate circuit 62b drives reset signal RSTT to the H level when power ondetection signal POR goes low or software reset signal SFRST goes high.

In memory circuit 50, a predetermined internal node 53 is provided witha resetting transistor 54. According to reset signal RSTT, predeterminedinternal node 53 is set to the ground voltage level by the resettingtransistor 54. Therefore, when internal node 53 is reset to the powersupply voltage VCC level upon the initialization, a P-channel MOStransistor (insulated gate field effect transistor) is used as theresetting transistor and the predetermined internal node 53 is connectedto the power supply node when the resetting P MOS transistor is madeconductive.

It is also possible to internally generate, according to software resetsignal SFRST, an array activating signal a predetermined number of timesand perform a dummy cycle of executing row selecting operation apredetermined number of times, thereby initializing the internal state.

FIG. 16 is a signal waveform diagram representing the operation ofstatus control circuit 22 shown in FIG. 15. Referring to the signalwaveform diagram shown in FIG. 16, the operation of status controlcircuit 22 shown in FIG. 15 will be briefly described below. After poweris on or at the time of recovery from power cutting off, the powersupply voltage VCC is supplied and the voltage level thereof increases.When the power supply voltage VCC reaches the predetermined voltagelevel, power on detection signal POR from power on detecting circuit 62abecomes the L level for a predetermined period of time and, accordingly,reset signal RSTT from gate circuit 62b goes high. Consequently, atpower on or recovery from power down, internal node 53 is reset to thepredetermined voltage level.

When the voltage level of internal node 53 is stabilized, software resetsignal SFRST is driven to the active state in accordance with thesoftware reset command. In this case as well, reset signal RSTT is setto the high level by gate circuit 62b, and the predetermined internalnode 53 is initialized to the ground voltage level in memory circuit 50.

By using software reset command (reset instruction signal) SFRST, thepower supply is cut off internally while the power supply voltage iscontinuously supplied externally in the power down mode, the internalnode can be reliably reset without using power on detection signal POR.By carrying out the software resetting after the voltage level of theinternal node is stabilized, the internal node can be initialized to apredetermined voltage level with reliability. Consequently,initialization of the internal node in the standby status andinitialization after completion of the standby status can be carried outwith reliability.

In the case where the semiconductor memory device is held in the standbystatus for a long period, the semiconductor memory device is set in adata holding mode, and storage data is internally refreshed according toa self refresh mode at predetermined intervals. By specifying the dataholding area in the refresh, only a necessary area is refreshed, andtherefore, the number of times of refreshing is reduced to reduce thecurrent consumption in the data holding mode.

FIG. 17 is a diagram schematically showing the correspondencerelationship between the memory cell array and data holding blockspecifying data. In FIG. 17, memory cell array 2 is divided into eightmemory array blocks MAB0 to MAB7. Memory blocks MAB0 to MAB7 aredesignated by data holding block specifying bits DHB0 to DHB7,respectively. Data holding block specifying bits DHB0 to DBH7 are set ina data holding register 70 in accordance with external data DQ0 to DQ7when a DHB selection mode is set.

In a DHB reading mode, data holding block specifying bits DHB0 to DHB7stored in data holding register 70 are read out externally.Specifically, when a DHB selection command is supplied and a DHBselection signal DHBS from command setting circuit 49 shown in FIG. 8goes high, data holding block specifying bits DQ0 to DQ7 stored in shiftregister 47 are stored in data holding register 70. When a DHB readcommand is supplied and a DHB read signal DHBR from command settingcircuit 49 shown in FIG. 8 is made active at the H level, the datastored in data holding register 70 is read out and supplied to an outputbuffer via the data bus switching circuit shown in FIG. 1, and outputexternally.

Data holding register 70 may be constructed of a latch circuit providedfor each data holding specifying bit or a set/reset flip flop disposedin correspondence with each data holding block specifying bit.

The data stored in data holding register 70 is supplied to a refreshcontrol circuit included in internal control signal generating circuit12 shown in FIG. 1 and an area to be refreshed is set.

In the case of specifying an area for holding data through therefreshing operation, according to a manner (specification) of settingthe data holding area, a method of specifying the refresh address areavaries. An example of a method of capable of setting whether data isheld or not for each of memory blocks MAB0 to MAB7 will be describedbelow.

FIG. 18 is a diagram schematically showing the configuration of arefresh control section included in internal control signal generatingcircuit 12 shown in FIG. 1. In FIG. 18, the refresh control sectionincludes: a refresh control circuit 72 for generating a refreshactivating signal RRAS at predetermined intervals; a refresh addresscounter 74 having a count value thereof sequentially updated undercontrol of refresh control circuit 72; a refresh block addressgenerating circuit 76 for generating a refresh block address forspecifying a refresh block in accordance with data holding area data(data holding block specifying bits) DHB0 to DHB7 and a count up signalCUP from refresh address counter 74; and a refresh address generatingcircuit 78 for generating a refresh address REFAD in accordance withoutput bits of refresh address counter 74 and output bits of refreshblock address generating circuit 76.

Refresh activating signal RRAS from refresh control circuit 72 issupplied to row circuitry related to an operation of selecting a rowsuch as a row decoder, a sense amplifier, and a row address buffer.Refresh address counter 74 generates an in-block address for specifyinga word line in a memory block, that is, a refresh word line address.

The count value of refresh counter 74 is updated each time therefreshing operation is completed. After completion of operation ofrefreshing data stored in memory cells in a memory block, refreshaddress counter 74 generates count up signal CUP.

Refresh block address generating circuit 76 designates the start refreshblock address in accordance with data holding area data (data holdingblock specifying bits) DHB0 to DHB7, performs shifting operation inaccordance with count up signal CUP, and sequentially generates arefresh block address for specifying the data holding block. In theshifting operation, according to refresh block specifying bits DHB0 toDHB7, the shifting operation bypasses memory blocks different from thedata holding area.

Therefore, when data holding block specifying bits DHB0 to DHB7 are “1”,for example, and the corresponding memory blocks are each designated asa data holding block, refresh block address generating circuit 76sequentially generates a block address for specifying a memory block asthe data holding area.

Refresh address generating circuit 78 receives, for adjusting timings,the refresh word line address from refresh address counter 74 and therefresh block address from refresh block address generating circuit 76and generates refresh address REFAD. Refresh address REFAD is suppliedto the row decoder via the row address buffer.

FIG. 19 is a diagram showing an example of the configuration of refreshblock address generating circuit 76 shown in FIG. 18. In FIG. 19,refresh block address generating circuit 76 includes: a highest bitposition detecting circuit 80 for detecting the position of the highestbit of bits “1” in data holding block specifying bits DBH0 to DBH7; ashift register 82 with a bypassing function which includes registerstages corresponding to memory blocks, initialized by highest bitposition detecting circuit 80, and performs shifting operation inaccordance with the count up signal and data holding area bits DBH0 toDBH7; and a block address register circuit 84 for sequentially selectinga block address in accordance with an output signal of shift register 82with the bypassing function and generating a refresh block addressRFBAD. In shift register 82 with the bypassing function, an output ofthe final stage is fed back to the input of the first register stage soas to perform shifting operation in a ring.

Highest bit position detecting circuit 80 is formed of a normaldetecting circuit for detecting the position of the highest bit of bits“1” in bits DBH0 to DBH7. When bits DBH0 to DBH7 are “1”, thecorresponding memory block are each designated as a data holding area.

Shift register 82 with the bypassing function has register stagesdisposed in correspondence with the memory blocks. The register stagecorresponding to the memory block in the highest position in the dataholding blocks is initially set to “1”. Shift register 82 with thebypassing function selectively executes the shifting operation inaccordance with the respective bits DBH0 to DBH7. Specifically, when acorresponding memory block is not designated as a data holding area, thecorresponding register stage is skipped and the shifting operation isexecuted between the register stages corresponding to the memory blocksdesignated as data holding areas.

Block address register circuit 84 stores a block address (of three bits)corresponding to a memory block and outputs the corresponding blockaddress when an output signal from shift register 82 with the bypassingfunction goes high.

FIG. 20 is a diagram schematically showing the configuration of one ofthe register stages of shift register 82 with the bypassing function.

An output of the final register stage in shift register 82 with thebypassing function is fed back to the first register stage.

In FIG. 20, the register stage includes: an AND circuit 82a receivingdata holding block specifying bit DBHi and count up signal CUP; a latchcircuit 82b for taking in data supplied from a preceding register stageand transferring the data to a subsequent register stage by performingtransferring operation using an output signal of AND circuit 82a as aclock signal; and a transfer gate 82c for short-circuiting the input andoutput of latch circuit 82b in accordance with data holding blockspecifying bit DBHi. Here, the reference “i” denotes any natural numberfrom 0 to 7 and indicates a memory block MBi.

The internal state of latch circuit 82b is set in accordance with acorresponding highest bit position detection signal MHPi from highestbit position detection circuit 80, and a corresponding selection signalSELi is set to H level when the latch circuit 82b is set. When dataholding area bit DBHi is at the H level (“1”), transfer gate 82c is inthe nonconductive state, and AND circuit 82a generates and applies anoutput signal to the latch circuit in accordance with count up signalCUP. In this case, therefore, latch circuit 82b performs operation oftransferring the signal. On the other hand, when data holding blockspecifying bit DBHi is “0” (L level), transfer gate 82c is renderedconductive and an output signal of AND circuit 82a is kept at the Llevel. Thus, latch circuit 82b is bypassed by transfer gate 82c and doesnot perform shifting operation. In this case, corresponding highest bitposition detection signal MHPi is at the L level and selection signalSELi normally is kept at the L level. Consequently, the block addresscan be activated only for the data holding area specified by dataholding block specifying bits DBH0 to DBH7.

In the case of initializing shift register 82 with the bypassingfunction in accordance with the output signal of highest bit positiondetection circuit 80, the initialization is executed in softwareresetting operation or DBH writing operation. Specifically, a one-shotpulse is generated when software resetting is performed or a DHB bit iswritten, and shift register 82 with the bypassing function isinitialized in accordance with output signal MHPi of highest bitposition detecting circuit 80.

FIG. 21 is a diagram showing an example of the configuration of blockaddress register circuit 84 shown in FIG. 19. In FIG. 21, block addressregister circuit 84 includes: register circuits RG0 to RG7 for storingblock addresses of memory blocks MB0 to MB7, respectively; and selectiongates TX1 to TX7 for selecting output signals of register circuits RG0to RG7 in accordance with selection signals SEL1 to SEL7 from shiftregister 82 with the bypassing function and generating a refresh blockaddress RFBAD. Selection gates TX1 to TX7 are provided in correspondencewith register circuits RG0 to RG7, respectively. One of selectionsignals SEL1 to SEL7 is maintained in an active state and one of theblock addresses stored in register circuits RG0 to RG7 is selected as arefresh block address.

In the configuration described above, the refresh block address isgenerated by block address register circuit 84 and supplied via the rowaddress buffer to the row decoder where decoding operation is performedon the refresh address. However, each of selection signals SEL1 to SEL7may be used as a memory row block selection signal. Specifically, such aconfiguration may be employed that in place of the row block selectionsignal for selecting a memory block in output signals from the rowdecoder, selection signals SEL1 to SEL7 are used as refreshing row blockselection signals and decoding operation for selecting a refresh row inthe selected memory row block is performed.

Second Embodiment

FIG. 22 is a diagram schematically showing the configuration of a mainportion of a second embodiment of the invention. In FIG. 22, theconfiguration of a main portion of command mode detecting circuit 30shown in FIG. 5A is shown.

In command mode detecting circuit 30 shown in FIG. 22, a 2-bit counter30i is provided in place of shift register 30b shown in FIG. 5A. Counter30i counts output signals of a gate circuit 30g receiving the decodesignal FAD and the read mode instruction signal φrz. A gate circuit 30mreceiving decode signal FAD and read instruction signal φrz and a gatecircuit 30n receiving an output signal of gate circuit 30m and writemode instruction signal φwz are provided in order to reset the counter30i.

Gate circuit 30g outputs an H level signal when decode signal FAD is atthe H level and read instruction signal φrz is at the L level. That is,gate circuit 30g detects that a read access is made to the finaladdress.

Gate circuit 30m outputs an H level signal when decode signal FAD is atthe L level and read instruction signal is at the L level. That is, gatecircuit 30m outputs a H level signal when a read access is made to anaddress other than the final address.

Gate circuit 30n outputs an H level signal to reset the counter 30i whenan output signal of gate circuit 30m goes high or write instructionsignal φwz goes low. When data is read/written from/to an address otherthan the final address, the count value of counter 30i is reset.

A carry bit CAR of counter 30i is stored in register circuit 30f (flipflop) shown in FIG. 5A.

In the configuration shown in FIG. 22, a gate circuit 30g detects a readaccess to the final address in accordance with decode signal FAD andread mode instruction signal φrz, and outputs an H level signal when theread access is made to the final address. Counter 30i counts the risingof an output signal of gate circuit 30g. That is, counter 30i counts thenumber of times of read accesses performed successively to the finaladdress.

On the other hand, in data reading operation, when decode signal FAD isat the L level, an output signal of gate circuit 30n goes high andcounter 30i is reset. In the case where data writing operation isperformed, write mode instruction signal φwz goes low, and counter 30iis similarly reset by gate circuit 30n.

When the final address is successively accessed for reading data apredetermined number of times, counter 30i sets carry bit CAR to the Hlevel, register (flip flop) 30f is set, and the command mode is set.

In the case of the configuration shown in FIG. 22, counter 30i can beconstructed of two stages of D latches, so that the circuit occupyingarea can be reduced as compared with the configuration using the dataregister.

Other Embodiments

In the foregoing description, data in the final address is read fourtimes successively to enter the command mode. In this case, the data ofthe final address is merely read out externally, and is not destructed.However, in the case where data stored in the final address is allowedto be destructed, the read and write modes may be appropriately combinedto perform the read and write modes a predetermined number of times forthe operation of setting the command mode. It is merely required toperform an operation sequence different from the operation sequenceexecuted in the normal operation mode.

The specific address is not limited to the final address, but may be anyaddress such as a start address or an intermediate address. Since thefrequency of using the final address in the normal operation mode islow, by accessing an address of low access frequency a predeterminednumber of times successively, the command mode entry mode and the normaloperation mode can be easily and reliably discriminated from each other.

The semiconductor memory device may be a semiconductor memory device forstoring 1-bit data by two DRAM cells. Specifically, complementary memorycell data are read out on a pair of bit lines, and a read voltagebetween the bit lines is set to a voltage twice as high as that in thecase of using a single memory cell for storing 1-bit data. In this case,a refresh interval can be made longer.

For setting the command mode, in place of the sequence of making anaccess for reading or writing with the final address designated, anyoperation sequence which is not used in the normal operation mode may beused. Specifically, a sequence of successively reading or writing datawith a specific address signal and a specific data bit set incombination to a predetermined state may be used for a command modeentry mode.

As described above, according to the present invention, a specificoperation mode is designated through a sequence which is not used in thenormal operation mode. Consequently, it is unnecessary to provide a newpin terminal for designating the specific operation mode. Thus, an SRAMalternative semiconductor memory device capable of maintainingcompatibility of pins with a conventional SRAM can be implemented.

Although the present invention has been described and shown in detail,it is clearly understood that the same is by way of illustration andexample only and is not to be taken by way of limitation, the spirit andscope of the present invention being limited only by the terms of theappended claims.

1. A semiconductor memory device comprising: mode detecting circuitryfor detecting that a predetermined set of external signals are appliedin a combination of specific logic states successively a plurality oftimes, said predetermined set of external signals including an addresssignal; and mode setting circuitry for setting a specific mode inresponse to a detection signal from said mode detecting circuitry. 2.The semiconductor memory device according to claim 1, wherein saidpredetermined set of external signals includes an address signal.
 3. Thesemiconductor memory device according to claim 2 1 wherein said addresssignal comprises a multiple of bits, and said combination of specificlogic states is a combination of states of the multiple bits of saidaddress signal designating a specific address.
 4. The semiconductormemory device according to claim 3, wherein said specific address is afinal address.
 5. The semiconductor memory device according to claim 21, wherein said predetermined set of external signals further includesan operation mode instruction signal.
 6. The semiconductor memory deviceaccording to claim 5, wherein said operation mode instruction signal isa read instruction signal for instructing a data reading operation. 7.The semiconductor memory device according to claim 1, further comprisingmode circuitry made operable in response to an output signal of saidmode setting circuitry in said specific mode, said mode circuitrygenerating, when a prescribed external signal in said external signalssatisfies a predetermined condition, a signal for designating aninternal state in accordance with other signals out of said externalsignals when made operable.
 8. A semiconductor memory device accessed inaccordance with external signals in a normal operation mode, comprising:a command decoder made active in a specific mode, for decodingpredetermined external signals out of said external signals andgenerating a signal for setting an internal state to a predeterminedstate when activated, said signal generated by said command decoderbeing a signal for designating an operation related to a standby statusof said semiconductor memory device, wherein said command decoderactivates any of a power down mode of designating cutting off of asupply of an internal power supply voltage, a wake up mode forcompleting said power down mode, a reset mode for setting the internalstate into an initial state, a mode of designating a data holding areain a data holding mode, and an exit mode for completing said specificmode in accordance with said predetermined external signals.
 9. Thesemiconductor memory device according to claim 8, wherein said specificmode is designated when an access in a sequence different from an accesssequence performed in said normal operation mode is made.
 10. Thesemiconductor memory device according to claim 8, wherein said specificmode is designated when a predetermined address is accessed apredetermined number of times successively.
 11. A semiconductor memorydevice accessed in accordance with external signals in a normaloperation mode, comprising: mode detecting circuitry for detecting thata predetermined set of external signals out of said external signals areapplied in a combination of specific logic states a plurality of timessuccessively, said predetermined set of external signals including anaddress signal, and said mode detecting circuitry detecting that saidaddress signal is applied in a state of designating a specific addresssaid plurality of times; mode setting circuitry for setting a specificmode in response to a detection signal of said mode detecting circuitry;and mode circuitry rendered operable in said specific mode in accordancewith an output signal of said mode setting circuitry.
 12. Thesemiconductor memory device according to claim 11, wherein saidpredetermined set of external signals includes an address signal, andsaid mode detecting circuitry detects that said address signal isapplied in a state of designating a specific address said predeterminednumber of times.
 13. The semiconductor memory device according to claim11, wherein said mode circuitry is a command decoding circuit fordecoding a command constructed of said predetermined set of externalsignals and generating an operation mode instruction signal inaccordance with a result of decoding, and said command decoding circuitactivates either of a power down mode of designating cutting off ofsupply of an internal power supply voltage, a wake up mode forcompleting said power down mode, a reset mode for setting an internalstate to an initial state, a mode of designating a data holding area ina data holding mode, and an exit mode for completing said specific mode.14. The semiconductor memory device according to claim 11, wherein saidmode circuitry generates a signal of designating an internal state inaccordance with an externally applied signal in said specific mode andsaid semiconductor memory device further comprises an internal statuscontrol circuit for setting an internal state to a state designated byan output signal of said mode circuitry in accordance with the outputsignal of said mode circuitry.
 15. The semiconductor memory deviceaccording to claim 14, wherein said mode circuitry generates, when aprescribed external signal in said external signals satisfies apredetermined condition, a signal for designating said internal state inaccordance with other signals out of said external signals.
 16. Thesemiconductor memory device according to claim 11, wherein said modecircuitry generates, when a prescribed external signal in said externalsignals satisfies a predetermined condition, a signal for designating aninternal state in accordance with other signals out of said externalsignals when made operable.
 17. The semiconductor memory deviceaccording to claim 6, further comprising a memory cell array having aplurality of memory cells arranged in rows and columns, wherein theaddress signal includes a row address signal designating a row of saidrows, and a column address signal designating a column of said columns,and said external signals further include a chip enable signal enablingsaid semiconductor memory device, and an output enable signal enablingdata output from said semiconductor memory device.
 18. The semiconductormemory device according to claim 17, wherein said specific mode includesa power down mode of cutting off a supply of a power to internalcircuitry in said semiconductor memory device.
 19. The semiconductormemory device according to claim 18, wherein said specific mode furtherincludes a wake up mode for completing said power down mode.
 20. Thesemiconductor memory device according to claim 17, wherein said specificmode further includes a reset mode for setting internal circuitry insaid semiconductor device to an initial state.
 21. The semiconductormemory device according to claim 17, wherein said specific mode furtherincludes a mode for designating a data holding region in said memorycell array in a data holding mode for holding storage data.
 22. Thesemiconductor memory device according to claim 17, wherein said specificmode further includes an exit mode for completing a set operation mode.23. The semiconductor memory device according to claim 17, wherein datacommunicated externally with said semiconductor memory device include anupper byte data and a lower byte data, and invalidation and validationof said upper byte data are controlled by an upper byte enable signaland invalidation and validation of said lower byte data is controlled byan upper byte enable signal.
 24. The semiconductor memory deviceaccording to claim 23, further comprising mode circuitry made operablein said specific mode in accordance with an output signal of said modesetting circuitry, said mode circuitry generating a signal designatingan internal state in said specific mode in accordance with externalsignals, and generating said signal designating said internal state inaccordance with the external signals including said upper byte data andsaid lower byte data, whichever is made valid, when a predeterminedsignal out of the external signals satisfies a prescribed condition. 25.The semiconductor memory device according to claim 11, wherein saidspecific address is a final address.
 26. The semiconductor memory deviceaccording to claim 25, further comprising a memory cell array having aplurality of memory cells arranged in rows and columns, wherein saidaddress signal includes a row address signal designating a row of saidrows, and a column address signal designating a column of said columns,and the external signals include a chip enable signal enabling saidsemiconductor memory device and an output enable signal enabling outputof data from said semiconductor memory device.
 27. The semiconductormemory device according to claim 26, wherein said specific mode includesa power down mode for cutting off a supply of a power to saidsemiconductor memory device.
 28. The semiconductor memory deviceaccording to claim 27, wherein said specific mode further includes awake up mode for completing said power down mode.
 29. The semiconductormemory device according to claim 26, wherein said specific mode furtherincludes a reset mode for setting an internal state of saidsemiconductor memory device to an initial state.
 30. The semiconductormemory device according to claim 26, wherein said specific mode furtherincludes a mode for designating a data holding region in said memorycell array for holding storage data in a data holding mode.
 31. Thesemiconductor memory device according to claim 26 wherein said specificmode further includes an exit mode for completing a set mode.